Memory – based Encoding Algorithm for Minimization of Inductive Cross-Talk based on Off- Chip Data Transmission

Inductive Cross-talk within IC Packaging is becoming a significant bottleneck in high speed inter chip communication. So the off-chip drivers typically source and sink 10 to 1000 drive internal loads. Thus simultaneously switching many off-chip drivers can cause large power (VDD) and ground current surges. These changes in current flow induce a voltage drop on the drivers’ local VDD rail and a voltage rise on the drivers’ local ground rail. The voltage drop is proportional to both the inductance of the VDD (ground) distribution network and the rate of change of the current flow (V= L * dl/dt). In this work, we proposed a technique to avoid the inductive cross-talk in the inter-connect by encoding the data being transmitted off-chip. Bus encoding algorithms have been developed to overcome the capacitive cross-talk for on-chip buses, so the problem of on-chip capacitive cross-talk minimization for busses is very different from that of off-chip inductive cross-talk minimization. In this paper our approach also constructs cross-talk resistant CODEC algorithmically to utilize the memory-based CODEC solution. Here we construct a set of equations which encoded the constraints that any legal vector sequence must satisfy to avoid supply bounce, signal glitching, and signal edge speed degradation. From this set of equations, we construct a set of legal vector sequences for the bus. We use this set to find the largest effective size of the bus that can be achieved by encoding, for a given physical size of the bus. Our experimental results show that the proposed encoding based techniques result in reduced supply bounce and signal degradation due to inductive cross-talk, closely matching the theoretical predictions. As a result the overall delay of the bus actually decreases even after the use of the encoding scheme.